The present invention relates generally to a structure of a thin film transistor (TFT), and more specifically to a structure of an amorphous-silicon (a-Si) thin film transistor array and its manufacturing method. The manufacturing method uses a two-step exposure (TSE) technology to reduce the number of photolithography process steps.
Generally, in a thin film transistor liquid crystal display (LCD) using an amorphous-silicon, a black resistance responsive to an OFF-state of the TFT is high, thereby increasing its switching efficiency. In addition, the TFT is formed at a low temperature and is applicable to a large-sized glass substrate, so that it is now being produced on a commercial scale as the main device. U.S. Pat. No. 5,545,576 discloses a manufacturing process of such a TFT panel. The TFT panel can reduce the number of steps in the manufacturing process and the occupation ratio of the TFT.
The method for manufacturing a TFT panel disclosed in U.S. Pat. No. 5,545,576 comprises (a) forming a gate electrode and a gate line on a transparent insulating substrate; (b) successively forming a gate insulating film, a semiconductor thin film and an insulating film on the gate electrode, the gate line and the transparent insulating substrate; (c) patterning the insulating film into a shape which is self-aligned with the gate electrode and the gate line by means of exposure through the transparent insulating substrate; (d) forming, on the insulating film, a mask having a length which extends across the gate electrode at right angles; (e) etching at least the insulating film and the semiconductor thin film using the mask; and (f) removing the mask, thereby forming a source electrode and a drain electrode.
At present, mass production of an amorphous-silicon thin film transistor usually takes six or seven (even more) photolithography process steps. Photolithography process, which is complicated and requires high precision, includes sequential process steps such as patterning a photo mask, coating photoresist, exposing, and developing. Therefore, reducing the number of masks needed in the manufacturing process can reduce the cost of production and particle contamination. The process flow of the conventional six-mask photolithography process for manufacturing amorphous-silicon thin film transistor comprises forming a gate electrode on a first metal (MI) layer, forming an active layer patterned as an island, making contact holes connecting the MI layer and a second metal layer, forming an indium-tin-oxide (ITO) layer, forming a source electrode and a drain electrode on a second metal (MII) layer, and forming a passivation layer.
In advanced amorphous-silicon thin film transistor manufacturing technologies, photolithography process is reduced to five-mask process flow. One of the manufacturing technologies is that the five masks are used sequentially in (a) an MI layer, (b) an active layer, (c) an MII layer, (d) a passivation layer, and (e) an ITO layer. The other is that the five masks are used sequentially in (a) an MI layer, (b) an active layer, (c) an MII layer, (d) contact holes and a passivation layer, and (e) an ITO layer.
U.S. Pat. No. 5,719,078 discloses a method for making a completely self-aligned thin film transistor panel of a liquid crystal display. The manufacturing method includes the steps of forming a gate electrode on a transparent substrate; depositing sequentially a gate insulating layer, a semiconductor layer and a first insulating layer; forming a channel protecting layer aligned with the gate electrode by patterning the first insulating layer; implanting ions into the semiconductor layer; depositing a conductive layer; patterning the conductive layer together with the semiconductor layer; forming a passivation layer including both a first opening and a second opening; forming a pixel electrode connected to the conductive layer through the second opening; and etching the conductive layer by using both the pixel electrode and the second insulating layer as a mask to form a source electrode and a drain electrode.
Five masks are needed for making a TFT disclosed in the above U.S. Pat. No. 5,719,078. The five masks are used sequentially in (a) a gate electrode, (b) a channel protecting layer, (c) a conductive layer and a semiconductor layer, (d) a passivation layer, and (e) a pixel electrode. The conductive layer and the semiconductor layer are patterned using a single mask in a single process step, thereby reducing the cost of production.
The primary object of the present invention is to provide a structure of an amorphous-silicon thin film transistor array for reducing the photolithography process steps as well as the number of photo-masks needed in manufacturing the thin film transistor array. Another object of the present invention is to provide a structure of an amorphous-silicon thin film transistor array for achieving better contact condition between MII and island layers. It is also an object of the present invention to provide a structure of an amorphous-silicon thin film transistor array for reducing the occurrence of open circuits in the MI layer or short circuits between MI and MII layers caused by the photoresist residue or particle contamination.
According to the invention, the structure of an amorphous-silicon thin film transistor array comprises (a) a substrate; (b) a gate electrode formed on the substrate; (c) a gate insulating layer formed on the gate electrode; (d) an amorphous-silicon active layer formed on the gate insulating layer; (e) an n+ amorphous-silicon layer formed on the active layer; and (f) a metal layer formed on the n+ amorphous-silicon layer for defining a source electrode and a drain electrode. The n+ amorphous-silicon layer and the metal layer have the characteristic of an island metal masking structure that can protect the active layer from plasma damage in plasma etching process.
In addition, this invention provides a method for making the amorphous-silicon thin film transistor array. The manufacturing method combines a conventional back-channel-etched (BCE) reduced mask process and a two-step exposure technology. The two-step exposure technology combines the island layer with the MII layer in a single process step, thereby reducing the process flow of the photolithography process.
According to the invention, the manufacturing method of an amorphous-silicon thin film transistor array comprises the following steps: (a) sputtering an MI layer and patterning thereon as a gate electrode on a substrate using a photo-mask by a photolithography process step; (b) sequentially depositing a gate insulating layer, an intrinsic amorphous-silicon layer and an n+ amorphous-silicon layer on the gate electrode and the entire substrate, and sputtering an MII layer on the entire substrate; (c) using the two-step exposure technology to combine an island layer with the MII layer in a single photolithography process step and forming a source electrode and a drain electrode on the MII layer; (d) forming a passivation layer on the entire substrate; and (e) forming an indium-tin-oxide layer on the passivation layer.
The two-step exposure technology of the invention in step (b) uses two photoresist pattern masks. One is pattern A mask for complete exposure. The other is pattern B mask for incomplete exposure. In the two-step exposure process, the photoresist is coated and exposed using pattern A mask with higher light intensity for complete exposure, and then exposed using pattern B mask with lower light intensity for incomplete exposure. Then the photoresist on pattern B is etched with O2 plasma etching. Steps (d) and (e) are completed by a conventional 5-mask Top ITO process method.
According to the invention, the advance process of the MII layer in step (b) can reduce the occurrence of open circuits in the MI layer or short circuits between the MI layer and the MII layer caused by the photoresist residue or particle contamination.
In the preferred embodiments of the invention, the general issues in two-step exposure process are the photoresist thickness and the thickness uniformity of the pattern B. The photoresist thickness is in the range of 1 xcexcm to 10 xcexcm. The light intensity for complete exposure is in the range of 30 mj/cm2 to 250 mj/cm2. The light intensity for incomplete exposure is in the range of 30 mj/cm2 to 150 mj/cm2. The thickness of the remaining photoresist in the channel region is in the range of 500 xc3x85 (Angstrom) to 50,000 xc3x85. Two modes of O2 plasma etching process used are plasma enhanced (PE) mode and reactive ion etching (RIE) mode.
The foregoing and other objects, features, aspects and advantages of the present invention will become better understood from a careful reading of a detailed description provided herein below with appropriate reference to the accompanying drawings.